National Journal of Advanced Research

ISSN: 2455-216X

Vol. 2, Issue 1 (2016)

Reduced control lines in multiplexer performing the ALU operation using QLUT

Author(s): Karthika P, Solomon Deva Doss S
Abstract: Digital design is an astounding and very massive field. The applicationsrnof digital design are exist in our day to day life, containing calculators,rncomputers, Mobiles, video cameras etc. The Aim of this paper is designing ALUrnand Reversible ALU. The ALU is mainly utilized in computer and is employedrnduring most instruction executions. Hence the power consumption of the ALU is arnmajor concern. Binary Digit Numbersrnare known to allow limited carry propagation with extra complex additionrnoperation. Limitations of this binary system are computational speed whichrnlimits formation and propagation of carry specifically when the number of bitsrnincreases. Design of binary logic circuits is easily possible when therninterconnection is less. As the immensernnumber of interconnection requirement has become a major limitation tornthe designs using binary logic. To overcome this problem by using Multiple-rnValued Logic (MVL). Quaternary logic proves to be advantageous as it reducesrndynamic power consumption, increases computational ability, data density andrnrequires less number of interconnects. So that the arithmetic unit design thisrngives better results than the binary circuits. It also produces higher information storage density, more exact arithmeticrnoperations and less complexity. This ALU consists of ten operations, fourrnarithmetic and six logical operations. The arithmetic operations includernaddition, subtraction, division and multiplication and the logical operationsrninclude NAND, AND, OR, NOT, shift and Rotation. Reversible ALU or Information-lossless circuits havernapplications in communication, computer graphics, digital signal processing andrncryptography. Reversibility used to prevents loss of information and energyrnefficient computations are considered. It operates at 195MHz frequencyrnat the same time as power consuming 52mW using Xilinx14.2 VHDL and thernsimulation results using ModelSim.
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